The present invention relates to a process for etching an organic material layer. It also relates to a process for producing interconnections of the damascene type incorporating a polymer dielectric layer. It more particularly applies to the field of interconnections for integrated circuits using copper as the conductive material.
A damascene structure is formed by the deposition, on one face to be connected to a microelectronic device to at least one dielectric material layer, by etching holes (for vertical interconnections) and trenches (for horizontal interconnections) in the dielectric material layer, by the deposition of a metallic layer on the etched dielectric material layer, and by polishing the metal excess in order to obtain the lines of. interconnections.
The improvement to the performance characteristics of integrated circuits (speed, low consumption) has led to a change in the materials used. To reduce the capacitance between the conductive lines, it is advantageous to use as the dielectric material certain organic materials, whose dielectric constant is lower than that of the insulating materials conventionally used, such as silicon dioxide.
The improvement to these performance characteristics is also linked to the use of a more conductive metal than the aluminum conventionally used for producing interconnection lines. The best candidate would appear to be copper, whose resistivity is twice as high as copperdoped aluminum. The use of intermediate layers has become necessary: a barrier layer with respect to the diffusion of copper, a polishing barrier layer, and a layer forming a hard mask.
The formation of the conductive lines of interconnections requires masking and etching operations with respect to the dielectric layers. When the dielectric layers were of mineral material, the removal of the masking resin caused no problem, because the removal processes did not have a detrimental influence on mineral layers. The use of organic material as the dielectric material in a damascene structure now gives rise to the problem of eliminating the masking resin without causing deterioration to the remainder of the structure and, in particular, the organic material dielectric layer.
This problem is illustrated by FIGS. 1A to 1C, which are partial cross-sectional views representing the production of a damascene type interconnection level.
FIG. 1A shows a metallic element 11 flush with the surface of a semiconductor device 10. The metallic element 11 is to be connected by a damascene type interconnection structure. A dielectric material layer 12 is first deposited on the surface of the semiconductor device. It is intended to house a conductive via permitting an electrical connection between the metallic element 11 and a connection line. On the layer 12 is deposited a layer 13 for forming a hard mask for the formation of the conductive via. The definition of the via hole is obtained by a resin mask 14 which, following the exposure and development stages, is in the form shown in FIG. 1A. The hole 15 in the resin mask 14 is aligned with the metallic element 11.
FIG. 1B shows the structure obtained after etching the layer 13 for forming the hard mask. The etching process leaves in the hard mask hole 16 with a diameter corresponding to the diameter of the hole 15 and revealing the layer 12. The following stage includes removing the resin mask. If the dielectric material layer 12 is a mineral material, this removal causes no problem. However, if the layer 12 is a polymer layer, the currently used removal methods (oxygen plasma, depolymerizing agent, solvent) give rise to a modification or consumption of the polymer. FIG. 1C shows that the removal of the resin mask has given rise to the formation of a damaged area 17 in the dielectric material layer 12.
An object of the present invention is to prevent the aforementioned problem. A first object of the invention relates to a process for etching an organic material layer. The process includes depositing an etching barrier layer on the organic material layer. The barrier layer is formed by a mineral material, i.e., an inorganic material. A masking layer is deposited on the barrier layer. The masking layer is formed by a mineral material, i.e., an inorganic material different from that of the barrier layer. A masking resin layer is deposited on the masking layer.
The process further includes forming an etching pattern in the resin layer used to expose the masking layer. The masking layer is etched in accordance with the etching pattern until the barrier layer is exposed. The masking resin layer is then removed, and the portion of the barrier layer that is exposed is etched until the organic material layer is exposed. The masking layer is removed, and the organic material layer is etched using the etched barrier layer as a mask.
Advantageously, the barrier layer etching stage and the masking layer elimination stage take place simultaneously. Optionally, following the stages of etching the barrier layer and eliminating the masking layer and before the stage of etching the organic material layer, at least one layer of a material which can be etched is deposited on the barrier layer.
A second object of the invention relates to a process for producing interconnections of the damascene type on a semiconductor device. The process includes depositing a first layer of an organic dielectric material on the surface to be connected to the semiconductor device. A second layer is deposited on the first layer. The second layer comprises a mineral material, i.e., an inorganic material, and is intended to serve as the etching barrier layer. A third layer is deposited on the second layer. The third layer comprises a mineral material, i.e., an inorganic material different from that of the second layer. A masking resin layer is deposited on the third layer.
The process further includes forming an interconnection pattern in the resin layer used to expose the third layer. The third layer is etched in accordance with the interconnection pattern until the second layer is exposed. The masking resin layer is then removed, and the portion of the second layer that is exposed is etched until the first layer is exposed. The third layer is removed, and the first layer is etched using the second layer as a mask. The etched portions are filled with an electrically conductive material.
Advantageously, the stages of etching the second layer and eliminating the third layer take place simultaneously. Preferably, the first layer is a polymer layer of very low permittivity. The second layer can be a SiO2 layer. The third layer can be a Si3N4 layer.
Following the stages of etching the second layer and eliminating the third layer and prior to the stage of etching the first layer, at least one layer of a material which can be etched may be deposited on the second layer. Thus, the process can also comprise the stages of depositing a fourth layer of an organic dielectric material on the second etched layer, and depositing a fifth layer on the fourth layer. The fifth layer comprises a dielectric material and serves as a hard mask. A masking resin layer is deposited on the fifth layer. The process further includes forming an interconnection pattern in the resin layer used to expose the fifth layer. The fifth layer is etched in accordance with the interconnection pattern until the fourth layer is exposed. The masking resin layer is then removed, and the portion of the fourth layer that is exposed is etched while using the fifth layer as a mask.
In this case, the etching stage of the fourth layer and the etching stage of the first layer can take place during a single operation. The stage of eliminating the masking resin deposited on the fifth layer, the etching stage of the fourth layer and/or the etching stage of the first layer can take place simultaneously. Advantageously, the fourth layer is a very low permittivity polymer layer. The fifth layer can be a SiO2 layer.